 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 features 2nd generation ee prom-based complex programmable logic devices ?v ccio of 5.0v or 3.3v with 3.3v operation being 5v tolerant ? 32 - 256 macrocells with enhanced features ? pin-compatible with industry standard devices ? speeds to 5 ns maximum pin-to-pin delay ? registered operation to 250 mhz enhanced macrocells with logic doubling ? features ? buryeitherregisterorcomwhileusingtheotherforoutput ? dual independent feedback allows multiple latch functions per macrocell ? 5 product terms per macrocell, expandable to 40 per macrocell with cascade logic, plus 15 more with foldback logic ? d/t/latch configurable flip-flops plus transparent latches ? global and/or per macrocell register control signals ? global and/or per macrocell output enable ? programmable output slew rate per macrocell ? programmable output open collector option per macrocell ? fast registered input from product term enhanced connectivity ? single level switch matrix for maximum routing options ? up to 40 inputs per logic block advanced power management features ? itd (input transition detection) available individually on global clocks, inputs and i/o for a level standby current for ?l? versions ? pin-controlled 1 ma standby mode ? reduced-power option per macrocell ? automatic power down of unused macrocells ? programmable pin-keeper inputs and i/os available in commercial and industrial temperature ranges available in all popular packages including plcc, pqfp and tqfp ee prom technology ? 100% tested ? completely reprogrammable ? 10,000 program/erase cycles ? 20 year data retention ? 2000v esd protection ? 200 ma latch-up immunity jtag boundary-scan testing port per ieee 1149.1-1990 and 1149.1a-1993 ? pull-up option on jtag pins tms and tdi ieee 1532 compatibility for fast in-system programmability (isp) via jtag pci-compliant security fuse feature atf15xxse family datasheet atf1502se(l) atf1504se(l) atf1508se(l) atf1516se(l) preliminary rev. 2401d?pld?09/02
2 atf15xxse family 2401d?pld?09/02 general description beginning with the introduction of the 100% connected atf1500 with 32 enhanced macrocells in 1996, atmel?s cpld products have delivered extra io connectivity and logic reusability. atmel?s commitment to efficient, flexible architecture has continued with the current atmel atf15xxse family of industry-standard, pin-compatible cplds. atmel?s logic doubling architecture consists of wider fan-in, additional routing and clock options, combined with sophisticated, proprietary device fitters, extend cpld place and route efficiency. atmel enhanced macrocell includes double independent buried feedback that allows designers to pack more logic (particularly shifters and latches) into a smaller cpld or leave spare room for later revisions. the atmel atf15xxse family delivers enhanced functionality and flexibility with no additional design effort and is highly cost effective. the atmel atf15xxse family includes all popular configurations and speeds. the atmel atf15xxse family includes pin-compatible products in all popular packages. notes: 1. contact atmel for up-to-date information on device and package availability. 2. when the jtag port is used for in system programming (isp) or boundary-scan testing (bst), the four associated pins become jtag pins and are unavailable for user i/o. table 1 . atf15xxse family device features feature atf1502se(l) atf1504se(l) atf1508se(l) atf1516se(l) usable gates 750 1500 3000 6000 macrocells 32 64 128 256 logic blocks 2 4 8 16 max. # pins 44 100 256 256 max. user i/os 36 68 100 164 t pd grades (ns) 5, 6, 7, 10(15) 5, 6, 7, 10(15) 6, 7, 10(15) 7, 10(15) table 2 . atf15xxse family device packages and number of signal pins (1)(2) packages atf1502se(l) atf1504se(l) atf1508se(l) atf1516se(l) 44-pin plcc 36 36 44-pin tqfp 36 36 84-pin plcc 68 68 100-pin tqfp 68 84 100-pin pqfp 84 160-pin pqfp 100 208-pin pqfp 164 208-pin rqfp 164 3 atf15xxse family 2401d?pld?09/02 functional description the atf15xxse family of 5.0 volt supply, high-performance, high-density complex program- mable logic devices (cplds) utilizes atmel?s proven electrically erasable non-volatile technology. with up to 512 macrocells, they easily integrate logic from several ttl, ssi, msi, lsi and classic plds. the atf15xxse family?s enhanced macrocell architecture, switch matrices and routing increase usable gate count for new designs and increase odds of suc- cessful pin-locked design modifications while maintaining pin-compatibility with industry standard cplds. the atf15xxse family devices have four dedicated input pins and depending on the type of device and package, up to 208 bi-directional i/o pins. each dedicated input pin can also serve as a global control signal, register clock, register reset or output enable. each of these control signals can be selected for use individually within each macrocell. each input and i/o pin also feeds into the global bus. the macrocells are organized into groups of sixteen called logic blocks. the switch matrix in each logic block selects 40 individual signals from the global bus. macrocells within a given logic block may share their sixteen foldback signals on a regional foldback bus. cascade logic between macrocells in the logic block allows fast, efficient generation of complex logic func- tions. all macrocells are capable of being i/os, however, the actual number of i/o pins depends on the device and package type. the atf15xxse family members contain two, four, eight, sixteen or thirty-two such logic blocks, each capable of creating sum term logic with a fan-in of 40 inputs from the switch matrix having access to up to 80 product terms. unused macrocells are automatically disabled by the fitter software to decrease power con- sumption. a security fuse, when programmed, protects the contents of the other fuses. two bytes (16 bits) of user signature are accessible to the user for purposes such as storing project name, part number, revision or date. the user signature is accessible regardless of the state of the security fuse. the atf15xxse family devices are in-system programmable (isp) devices. they use the industry-standard 4-pin jtag interface (ieee std. 1149.1), and are fully-compliant with jtag?s boundary-scan description language (bsdl). isp allows the device to be pro- grammed without removing it from the printed circuit board. in addition to simplifying the manufacturing flow, isp also allows design modifications to be made in the field via software. global bus/switch matrix the global bus (figure 1) contains all input and i/o pin signals as well as the buried feedback signals from all macrocells. the switch matrix in each logic block receives as its inputs all sig- nals from the global bus. up to 40 of these signals can be selected as inputs to the individual logic blocks by the fitter software. atmel?s atf15xx family of cplds use a single level switch matrix signal distribution structure, where each logic block input has access to the same num- ber of global bus inputs, maximizing the number of possible ways to route a global bus signal. this single level structure is in contrast with split switch matrix structures used by others in which routing a particular global bus input to a particular logic block input makes that signal unavailable to some other logic blocks, thus greatly limiting the available opportunities to route. the atf15xxse family macrocell, shown in figure 2, consists of five sections: product terms and product term select multiplexer, or/xor/cascade logic, foldback bus, a flip-flop and output buffer. extra fan-in and signal routing are provided throughout. each macrocell can generate a foldback logic term from the product term mux and a buried feedback with extra routing that go to the global bus. 4 atf15xxse family 2401d?pld?09/02 figure 1. atf15xxse family typical block diagram 6to16 n n-1 6to16 5 atf15xxse family 2401d?pld?09/02 figure 2. atf15xxse family macrocell with enhanced features in red product terms and select mux within each macrocell are five product terms. each product term may receive as its inputs any combination of the signals from the switch matrix or regional foldback bus. the product term select multiplexer (ptmux) allocates the five product terms as needed to the macrocell logic gates and control signals. the ptmux programming is determined by the fitter software, which selects the optimum macrocell configuration. or/xor/ cascade logic withinasinglemacrocell,alltheproducttermscanberoutedtotheorgate,creatinga5- input and/or sum term. with the addition of the casin from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. the macrocell?s xor gate allows efficient implementation of compare and arithmetic func- tions. one input to the xor comes from the or sum term. the other xor input can be a product term or a fixed high- or low-level. for combinatorial outputs, the fixed level input allows polarity selection. for registered functions, the fixed levels allow demorgan minimiza- tion of product terms. the xor gate may be fed from the flip-flop output to emulate t- and jk- type flip-flops, or fed to the buried feedback to synthesize an extra latch. foldback bus each macrocell can also generate a foldback product term. this signal goes to the regional bus and is available to the 16 macrocells in a given logic block. the foldback is an inverse polarity of one of the macrocell?s product terms. although cascade logic is the preferred method for expanding the number of macrocell inputs to as many as 40, the 16 foldback terms in each region can also generate additional fan-in sum terms with nominal additional delay. regional foldback bus 16 logic foldback i/o pin 3 gck[0:2] gclear casout d/ t*/l ce ar ap q casin i/o pin slew rate open collector 6 goe[0:5] reduced power option s w i t c h m a t r i x 80 global bus 40 1 2 3 4 5 p r o d u c t t e r m m u x pt1 pt2 pt3 pt5 pt4 switch matrix outputs * t flip-flop synthesised !q q !q ck/ck /le goe switch matrix goe [0:5] 6 atf15xxse family 2401d?pld?09/02 flip-flop the atf15xxse family?s flip-flop has very flexible data and control functions. the data input can come from either the xor gate, from a separate product term or directly from the i/o pin. selecting the separate product term allows creation of a buried registered feedback within a combinatorial output or vice-versa. (this enhanced function is automatically implemented by the fitter software). the flip-flop can be configured for d, t, jk and sr operation, and changes state on the clock?s rising edge. it can also be configured as a flow-through latch. in this mode, data passes through when the clock is high and is latched when the clock is low. when a gck signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. when the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. the flip-flop has asynchronous reset and preset. the flip-flop?s asynchronous reset signal (ar) can be either the global clear (gclear), a product term, or always off. ar can also be a logic or of gclear with a product term. the asynchro- nous preset (ap) can be a product term or always off. extra feedback the atf15xxse family macrocell output can be selected as registered or combinatorial. the extra buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered. (this enhanced function is automatically implemented by the fitter software) feedback of a buried combinatorial output allows the cre- ation of a second latch within a macrocell. i/o control the output enable multiplexer (moe) controls the output enable signal. each i/o can be indi- vidually configured as an input, output or for bi-directional operation. the output enable for each macrocell can be selected from the true or compliment of the two output enable pins, a subset of the i/o pins, or a subset of the i/o macrocells. this selection is automatically done by the fitter software when the i/o is configured as an input, all macrocell resources are still available, including the buried feedback, expander and cascade logic. the buffer has a fast/slow slew rate option to control emi and an open-collector option which enables the device to provide control signals such as an interrupt that can be asserted by any of the several devices. programmable pin-keeper option for inputs and i/os the atf15xxse family offers the option of programming all input and i/o pins with pin-keeper circuits enabled. when any pin is driven high or low and then subsequently left floating, the pin keeper circuit will hold it at that previous high or low-level. this circuitry prevents unused input and i/o lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. the pin-keeper circuits eliminate the need for external pull-up resistors and eliminate their dc power consumption. 7 atf15xxse family 2401d?pld?09/02 input diagram i/o diagram speed/power management the atf15xxse family has several speed and power management features. multiple power supplies, power sequencing and hot-socketing because the atf15xxse family can be used in a system with mixture of power supplies, it has been designed to function with the v ccint and v ccio power supplies applied in any sequence. also, until the power up sequence completes, the input/output buffers are kept in a high impedance state, and so may be driven but do not drive power out. programmable option (pin keeper) programmable option (pin keeper) 8 atf15xxse family 2401d?pld?09/02 power-on reset the atf15xx family devices are designed with a power-on reset, a feature critical for state machine initialization. at a point delayed slightly from v cc crossing v rst , all registers will be initialized, and the state of each output will depend on the polarity of its buffer. however, due to the asynchronous nature of reset and uncertainty of how v cc actually rises in the system, the following conditions are required: 1. the v cc rise must be monotonic, 2. after reset occurs, all input and feedback setup times must be met before driving the clock pin high, and, 3. the clock must remain stable during t d . the atf15xx family has two options for the hysteresis about the reset level, v rst ,smalland large. in applications where the supply voltage may drop below 4.0v, atmel recommends that during the fitting process users configure the device with the power-on reset hysteresis set to large to ensure a robust operating environment. power down of unused macrocells to conserve power, atmel fitters automatically power down all unused macrocells. input transition detection/ automatic power down the atf15xxsel versions provide automatic power-down to a level stand-by power (the ?l? suffix indicates ?low? power) through atmel?s patented input transition detection (itd) cir- cuitry on global clocks, inputs and i/o. these itd circuits automatically put the device into a low-power standby mode when no logic transitions are occurring. this reduces power con- sumption during inactive periods, and so provides proportional power savings for most applications running at system speeds below f critical (~5 mhz). in clocked applications, where the device is operated at a frequency high enough to keep the device from going into stand-by (above f critical ), the device will perform at the faster speeds given in the next faster speed column. these higher speeds can be achieved in combinatorial designs as well, as long as once activated by an initial input transition, the device continues to receive input transitions often enough to keep the device from going into standby mode again. that is, the time between input transitions is less than 1/f critical . reduced-power per macrocell to further reduce power, each atf15xxse family macrocell has a reduced-power bit feature. with this feature the designer can reduce power by 50% or more for logic that does not need to operate at the maximum switching speed. the reduced-power bit may be activated by changing the default off to on for any or all macrocells. for macrocells in reduced-power mode (reduced-power bit turned on), the reduced- power adder, t rpa , must be added to the ac parameters, which include the data paths t lad ,t lac ,t ic ,t acl ,t ach and t sexp . all power-down ac characteristic parameters are computed from external input or i/o pins, with the reduced- power bit turned on. slew rate control each output also has individual slew rate control. this may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. outputs default to slow switching. the slew rate option is selected in the design source file. pin controlled power-down all atf15xx family devices also have an optional pin-controlled power-down mode. when activated, one or both of two pins, pd1 and pd2, can act as power-down pins. the device goes into power-down when either pd1 or pd2 pins (or both) are high, and the device supply current is reduced to less than 1 ma. also, all internal logic signals are latched and held, as are any enabled outputs. therefore, all registered and combinatorial output data remain valid. any outputs that were in a high-z state at the onset will remain at high-z. input and i/o hold 9 atf15xxse family 2401d?pld?09/02 latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. all pin transitions are ignored until the pd pin is brought low. when the power- down feature is enabled for pd1 or pd2, that pin cannot be used as a logic input or output. however, the pin?s macrocell may still be used to generate buried foldback and cascade logic signals. the power-down option is selected in the design source file. power consumption estimates an estimate of power consumption can be made based on typical designs and operation con- ditions, but because it is sensitive to these factors, power consumption must be verified with actual pattern and operation conditions. the equations given below are based on a pattern of 16-bit up/down counters in each logic block and may be used to estimate power consumption for both operating modes. standby power 1. p standby =i ccstandby xv supply where: i ccstandby = the standby current given for the particular device and standby mode (e.g. pin con- trolled power down) v supply = the power supply voltage active power 2. p active =p internal +p load =i ccinternal xv supply +p load where: i ccinternal = the internal current estimated from equation 3 below v supply = the power supply voltage p load = depends on the device output load capacitance and switching frequency on each out- put pin. p load and additional power savings at low frequencies using atmel input transition detection (?l? versions) can be estimated according to the methods discussed in the atmel application note ?saving power with atmel plds? 3. i ccinternal =[k 1 x(mc inuse ? mc reducedpower )] + (k 2 xmc reducedpower )+(k 3 xmc inuse xf op x ns) where: mc reducedpower = the number of macrocells operating at reduced power (from fitter report file) mc inuse = the number of macrocells in use (from fitter report file. unused macrocells are pow- ered down.) ns = the proportion of logic nodes switching (typically 10-20%) f op = the switching frequency k 1 ,k 2, and k 3 = device constants given in the table below. note: shaded data is preliminary and subject to change without notice. device k 1 (ma/mc) k 2 (ma/mc) k 3 (ma/mc mhz) atf1502se 0.6 0.3 0.015 atf1504se 0.6 0.3 0.015 atf1508se 0.6 0.3 0.015 atf1516se 0.6 0.3 0.015 10 atf15xxse family 2401d?pld?09/02 design software atmel atf15xxse family fitters allow logic synthesis using a variety of high-level description languages and formats. atf15xxse family designs are supported by atmel specific design tools as well as by several third-party tools. free conversion software is also offered for indus- try standard devices. check the atmel web site or contact your authorized atmel sales representative for up-to-date design software information. programming atf15xxse family devices can be programmed using standard third-party programmers. with third-party programmers, the jtag isp port can be disabled thereby allowing four addi- tional i/o pins to be used for logic. check the atmel web site, contact your authorized atmel sales representative or atmel pld applications for details of third-party programmers. atf15xxse family devices are in-system programmable (isp) devices ut ilizing the 4-pin jtag protocol. this capability eliminates package handling normally required for program- ming and facilitates rapid design iterations and field changes. atmel provides isp hardware and software to allow programming of the atf15xxse family via the pc. isp is performed by using either a download cable, a compatible board tester or a simple microprocessor interface. it is most common to devote the jtag pins to isp, but it is possible to use isp to program the part through the jtag pins, and set these four pins i/o pins. however, this will effectively dis- able further isp and the device will need to be erased on a programmer to re-enable isp. contact atmel pld applications by email at pld@atmel.com or call our hotline at (408) 436- 4333 for details. to allow isp programming support by the automated test equipment (ate) vendors, serial vector format (svf) files can be created by the atmel isp software. conversion to other ate tester formats is also possible. check the atmel web site for up-to-date programming and soft- ware support information. isp programming protection the atf15xxse family also incorporates a protection feature that locks the device and pre- vents the inputs and i/o from driving if the programming process is interrupted for any reason. the inputs and i/o default to high-z state during such a condition. in addition the pin-keeper option preserves the former state during device programming. all atf15xxse family devices are initially shipped in the erased state thereby making them ready to use for isp. for more information refer to the ?designing for in-system programmability with atmel cplds? application note. security fuse usage a single fuse is provided to prevent unauthorized copying of the atf15xxse family fuse pat- terns. once programmed, fuse verify is inhibited. however, the user signature and device id remain accessible. 11 atf15xxse family 2401d?pld?09/02 jtag-bst overview the jtag-bst (jtag boundary-scan testing) is controlled by the test access port (tap) controller. the boundary-scan technique involves the inclusion of a shift-register stage (con- tained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. each input pin and i/o pin has its own boundary-scan cell (bsc) in order to support boundary-scan testing. the atf15xxse family does not currently include a test reset (trst) input pin because the tap controller is automatically reset at power-up. the atf15xxse family implements six bst instructions, and seven atmel-defined in system programming (isp) instructions. all atf15xx family bst and isp instructions have a length of 10 bits. the atf15xxse family bst implementation complies with the boundary-scan definition lan- guage (bsdl) described in the jtag specification (ieee standard 1149.1). any third-party tool that supports the bsdl format can be used to perform bst on the atf15xxse family. the atf15xxse family also has the option of using four jtag-standard i/o pins for in-system programming (isp). the atf15xxse family is programmable through the four jtag pins using programming-compatible with the ieee jtag standard 1149.1. programming is per- formed by using 5v ttl-level programming signals from the jtag isp interface. the jtag feature is a programmable option. if jtag (bst or isp) is not needed, then the four jtag control pins are available as i/o pins. refer to atmel application note ?designing for in-sys- tem programmability with atmel cplds for more details. jtag bst instructions description sample/preload captures signals at the device pins for later examination, or loads a data pattern prior to an extest instruction. extest allows testing of off-chip circuitry and interconnections by forcing a pattern on the output pins or capturing signals from the input pins. bypass places a single shift register stage between tdi and tdo, allowing test bst data to pass through a particular device in a chain of devices. idcode places the 32-bit idcode register between tdi and tdo, allowing the idcode data to be shifted out of tdo. uescode places the 16-bit user electronic signature register between tdi and tdo, allowing the uescode data to be shifted out of tdo. highz places the bypass register between tdi and tdo in a high impedance mode, protecting the device from damage from externally applied test signals. 7 isp instructions these seven instructions allow in-system programming via the four jtag pins. 12 atf15xxse family 2401d?pld?09/02 jtag boundary-scan cell (bsc) testing the atf15xxse family has four dedicated input pins and a number of i/o pins depending on the device type and package type selected. each input pin and i/o pin has a boundary-scan cell (bsc) which supports boundary-scan testing as described in detail by ieee standard 1149.1. a typical bsc consists of three capture registers or scan registers and up to two update registers. there are two types of bscs, one for input or i/o pin, and one for the macro- cells. the bscs in the device are chained together through the (bst) capture registers. input to the capture register chain is fed in from the tdi pin while the output is directed to the tdo pin. capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. control signals are generated internally by the jtag tap controller. note: shaded data is preliminary and subject to change without notice. boundary-scan definition language (bsdl) models these are now available in all package types via the atmel web site. these models conform to the ieee 1149.1 standard and can be used for boundary-scan test operation of the atf15xxse family. the bsc configuration for the input and i/o pins and macrocells are shown on page 13. device boundary-scan register length idcode msb lsb atf1502se 96 0000,0001,0101,0100,0010,0000,0011,1111 atf1504se 192 0000,0001,0101,0100,0100,0000,0011,1111 atf1508se 352 0000,0001,0101,0100,1000,0000,0011,1111 atf1516se 672 0000,0001,0101,0101,0000,0000,0011,1111 13 atf15xxse family 2401d?pld?09/02 bsc configuration for pins (except jtag tap pins) bsc configuration for macrocell 0 1 0 1 dq dq capture register update register 0 1 0 1 dq dq tdi outj oej shift clock mode tdo macrocell bsc pin 14 atf15xxse family 2401d?pld?09/02 pci compliance the atf15xx family also supports peripheral component interconnect (pci) interface stan- dard in pci-based designs and specifications. the pci interface calls for high current drivers, which are much larger than the traditional ttl drivers. pci voltage-to- current curves for +5v signaling in pull-up mode pci voltage-to- current curves for +5v signaling in pull-down mode 2.4 vcc 1.4 -2 -44 -178 current (ma) ac drive point dc drive point voltage pull up test point 2.2 vcc 0.55 3,6 95 380 current (ma) ac drive point dc drive point voltage pull down test point 15 atf15xxse family 2401d?pld?09/02 pci dc characteristics note: leakage current is without pin-keeper off. pci ac characteristics notes: 1. equation a: i oh =11.9(v out - 5.25) * (v out + 2.45) for v cc >v out >3.1v. 2. equation b: i ol = 78.5 * v out *(4.4-v out )for0v 16 atf15xxse family 2401d?pld?09/02 note: 1. junction temperature is package and device dependant and can be calculated as follows: t j(max) =t a(max) +( ja | air flow = 0 *p (max) ). for more information see ?thermal characteristics of atmel packages.? absolute maximum ratings* ambient temperature under bias.................. -65c to +135c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. for currents less than 100 ma, minimum voltage is -0.6 vdc and maximum voltage is v cc + 0.75 vdc. pulses of less than 20s may under- shoot to -2.0v or overshoot to 7.0v. storage temperature ..................................... -65c to +150c junction temperature ..............................................150c (max) voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) dc output current per pin ................................ -25 to +25 ma dc and ac operating conditions commercial industrial operating temperature (ambient), t a 0c - 70c -40c - 85c junction temperature, t j (1) ?? v ccint (5.0v) power supply 5v 5% 5v 10% v ccio (5.0v) power supply 5v 5% 5v 10% v ccio (3.3v) power supply 3.0 - 3.6 3.0 - 3.6 v i input voltage -0.5 - v ccint +.5 -0.5-v ccint +.5 v o output voltage 0 - v ccio 0-v ccio t r 40 ns max 40 ns max t f 40 ns max 40 ns max 17 atf15xxse family 2401d?pld?09/02 notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. i cc3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on. 3. see characteristic curves for each device. notes: 1. for slow slew outputs, add t sso . 2. pin or product term. dc characteristics (1) atfxxse family symbol parameter condition min typ min unit i il input or i/o low leakage current v in =v cc -2 -10 a i ih input or i/o high leakage current 2 10 a i oz tri-state output off-state current v o =v cc or gnd -40 40 a i cc1 power supply current, standby v cc =max v in =0,v cc std mode com. (3) ma ind. (3) ma ?itd? mode com. 1 ma ind. 1 ma i cc2 power supply current, power-down mode v cc =max v in =0,v cc pd mode 0.1 1 ma i cc3 (2) reduced-power mode supply current, standby v cc =max v in =0,v cc std mode com. (3) ma ind. (3) ma v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 v ccint +0.5 v v ol 5.0v output low voltage (ttl) i ol =12ma,v ccio = 4.75v 0.45 v 3.3v output low voltage (ttl) i ol =12ma,v ccio =3.0v 0.45 v 3.3v output low voltage (cmos) i ol =0.1ma,v ccio =3.0v 0.2 v v oh 5.0v output high voltage (ttl) i oh =-4ma,v ccio = 4.75v 2.4 v 3.3v output high voltage (ttl) i oh =-4ma,v ccio = 3.0v 2.4 v 3.3v output high voltage (cmos) i oh =-0.1ma,v ccio =3.0v v ccio ?0.2 v power-down ac characteristics (1) atfxxse family symbol parameter -5 -6 -7 -10 -15 unit min max min max min max min max min max t ivdh valid 1, i/o before pd high 5.0 6.0 7.0 10 15 ns t gvdh valid 1, oe (2) before pd high 5.0 6.0 7.0 10 15 ns t cvdh valid 1, clock (2) before pd high 5.0 6.0 7.0 10 15 ns t dhix i, i/o don?t care after pd high 9.0 10.0 12 15.0 25 ns t dhgx oe (2) don?t care after pd high 9.0 10.0 12 15.0 25 ns t dhcx clock (2) don?t care after pd high 9.0 10.0 12 15.0 25 ns t dliv pd low to valid i, i/o 1.0 1.0 1.0 1.0 1.0 s t dlgv pd low to valid oe, (pin or term) 1.0 1.0 1.0 1.0 1.0 s t dlcv pd low to valid clock, (pin or term) 1.0 1.0 1.0 1.0 1.0 s t dlov pd low to valid output 1.0 1.0 1.0 1.0 1.0 s 18 atf15xxse family 2401d?pld?09/02 timing model note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. the ogi pin (high-voltage pin during programming) has a maximum capacitance of 12 pf. input test waveforms and measurement levels output ac test loads pin capacitance typ (1) max units condition c in 810pfv in =0v;f=1.0mhz c i/o 810pfv out =0v;f=1.0mhz u (3.3v) 464 250 (703 ) (8060 ) 5.0v c=c l 19 atf1502se 2401d?pld?09/02 ac characteristics (1) atf1502se(l) symbol parameter se -5 se -6 se -7 se -10 sel -15 (6) unit min max min max min max min max min max t pd1 input or feedback to non- registered output 5.0 6.0 7.5 10 15 ns t pd2 i/o input or feedback to non- registered feedback 5.0 6.0 7.5 10 12 ns t su global clock setup time 2.9 4.0 5.0 7.0 11 ns t h global clock hold time 0.0 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 2.5 2.5 3.0 3.0 ns t fh global clock hold of fast input 0.0 0.0 0.0 0.0 1.0 ns t co1 global clock to output delay 3.2 3.5 4.3 5.0 8.0 ns t ch global clock high time 2.0 2.5 3.0 4.0 5.0 ns t cl global clock low time 2.0 2.5 3.0 4.0 5.0 ns t asu array clock setup time 0.7 0.9 1.1 2.0 4.0 ns t ah array clock hold time 1.8 2.1 2.7 3.0 4.0 ns t aco1 array clock output delay 5.4 5.4 6.6 8.2 15 ns t ach array clock high time 2.5 2.5 3.0 4.0 6.0 ns t acl array clock low time 2.5 2.5 3.0 4.0 6.0 ns t cnt minimum clock global period 5.7 7.0 8.6 10.0 13 ns f cnt (3) maximum internal global clock frequency 175.4 143 117 100 77 or 100 (6) mhz t acnt minimum array clock period 5.7 7.0 8.6 10.0 13 ns f acnt (4) maximum internal array clock frequency 175.4 143 117 100 77 or 100 (6) mhz f max (5) maximum clock frequency 250 200 167 125 80 or 125 (6) mhz t in input pad and buffer delay 0.2 0.2 0.3 0.5 1.0 ns t io i/o input pad and buffer delay 0.2 0.2 0.3 0.5 1.0 ns t fin fast input delay 2.2 2.1 2.5 1.0 1.5 ns t sexp foldback term delay 3.1 3.8 4.6 5.0 8.0 ns t pexp cascade logic delay 0.9 1.1 1.4 0.8 1.0 ns t lad logic array delay 2.6 3.3 4.0 5.0 6.0 ns t lac logic control delay 2.5 3.3 4.0 5.0 6.0 ns t ioe internal output enable delay 0.7 0.8 1.0 2.0 3.0 ns t od1 output buffer and pad delay (slow slew rate = off; v ccio = 5v; c l =35pf) 0.2 0.3 0.4 1.5 2.5 ns 20 atf1502se 2401d?pld?09/02 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad ,t lac ,t ic ,t acl and t sexp parameters for macrocells running in the reduced- power mode. 3. f cnt is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a pia fan-out of one logic block (16 macrocells). f cnt is also the export control maximum flip-flop toggle rate, f to g . 4. f acnt is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a pia fan-out of one logic block (16 macrocells). 5. f max is the fastest available frequency for pipelined data. 6. for clocked applications and frequencies above f critical , or, non-clocked applications with dormant times less than 1/f crit- ical , the device will achieve the speeds of the ?10 column. see ?input transition detection/ automatic power down? on page 8. t od2 output buffer and pad delay (slow slew rate = off; v ccio = 3.3v; c l =35pf) 0.7 0.8 0.9 2.0 3.0 ns t od3 output buffer and pad delay (slow slew rate = on; v ccio =5v or 3.3v; c l =35pf) 5.2 5.3 5.4 5.5 6.0 ns t zx1 output buffer enable delay (slow slew rate = off; v ccio = 5v; c l =35pf) 4.0 4.0 4.0 5.0 7.0 ns t zx2 output buffer enable delay (slow slew rate = off; v ccio = 3.3v; c l =35pf) 4.5 4.5 4.5 5.5 7.0 ns t zx3 output buffer enable delay (slow slew rate = on; v ccio =5v or 3.3v; c l =35pf) 9.0 9.0 9.0 9.0 10 ns t xz output buffer disable delay (c l =5pf) 4.0 4.0 4.0 5.0 6.0 ns t su register setup time 0.8 1.0 1.3 2.0 4.0 ns t h register hold time 1.7 2.0 2.5 3.0 4.0 ns t fsu register setup time of fast input 1.9 1.7 1.7 3.0 5.0 ns t fh register hold time of fast input 0.6 0.7 0.8 0.5 2.0 ns t rd register delay 1.2 1.6 1.2 2.0 2.0 ns t comb combinatorial delay 0.9 1.1 1.0 2.0 2.0 ns t ic array clock delay 2.7 3.4 2.0 5.0 7.0 ns t en register enable time 2.6 3.3 1.0 5.0 7.0 ns t glob global control delay 1.6 1.4 1.3 1.0 1.0 ns t pre register preset time 2.0 2.4 1.9 3.0 5.0 ns t clr register clear time 2.0 2.4 3.0 3.0 5.0 ns t uim switch matrix delay 1.1 1.1 1.4 1.0 2.0 ns t rpa (2) reduced power adder 8 9 10 11 13 ns ac characteristics (1) atf1502se(l) (continued) symbol parameter se -5 se -6 se -7 se -10 sel -15 (6) unit min max min max min max min max min max 21 atf1502se 2401d?pld?09/02 stand-by i cc vs. supply voltage (t a =25c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.54.85.05.35.5 supply voltage (v) i cc (a) tbd supply current vs. input frequency (v cc =5.0v,t a = 25c) 0.000 20.000 40.000 60.000 80.000 100.000 120.000 140.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz ) i cc (ma) tbd output source current vs. supply voltage (v oh =2.4v) -50 -40 -30 -20 -10 0 4.04.55.05.56.0 supply voltage (v) i oh (ma) tbd output sink current vs. supply voltage (v ol =0.5v) 36 38 40 42 44 46 48 4.0 4.5 5.0 5.5 6.0 supply voltage (v) iol (ma) tbd normalized i cc vs. temp 0.4 0.6 0.8 1.0 1.2 1.4 -40.0 0.0 25.0 75.0 temperature (c) normalized icc tbd supply current vs. input frequency (v cc =5.0v,t a = 25c) 0.000 0.200 0.400 0.600 0.800 1.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. output voltage (v cc =5.0v,t a = 25c) -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 v oh (v) i oh (ma) tbd output sink current vs. output voltage (v cc =5.0v,t a =25c) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) i ol (ma) tbd 22 atf1502se 2401d?pld?09/02 input clamp current vs. input voltage (v cc =5.0v,t a =35c) -120 -100 -80 -60 -40 -20 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 input voltage (v) input current (ma) tbd normalized t pd vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t pd tbd normalized t co vs. vcc 0.8 0.9 1.0 1.1 1.2 1.3 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t co tbd normalized t su vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t su tbd input current vs. input voltage (v cc =5.0v,t a = 25c) -30 -20 -10 0 10 20 30 40 0.0 1.0 2.0 3.0 4.0 5.0 6.0 input voltage (v) input current (ua) tbd normalized t pd vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (c) normalized t pd tbd normalized t co vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (v) normalized t co tbd normalized t su vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized t co tbd 23 atf1502se 2401d?pld?09/02 delta t pd vs. output loading -2 0 2 4 6 8 0 50 100 150 200 250 300 output loading (pf) delta t pd (ns) tbd delta t pd vs. # of output switching -0.5 -0.4 -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t pd (ns) tbd delta t co vs. output loading 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 50 100 150 200 250 300 number of outputs loading delta t co (ns) tbd delta t co vs. # of output switching -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t co (ns) tbd 24 atf1502se 2401d?pld?09/02 atf1502se(l) pinouts 44-lead tqfp - top view 44-lead plcc - top view 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 tdi/i/o i/o i/o gnd pd1/i/o i/o i/o/tms i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 i/o i/o i/o i/o gnd vcc i/o pd2/i/o i/o i/o i/o i/o i/o i/o vcc gck2/oe2/i gclr/i oe1/i gck1/i gnd i/o/gclk3 i/o atf1502se(l) atf1504se(l) 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 i/o/tdi i/o i/o gnd pd1/i/o i/o tms/i/o i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 i/o i/o i/o i/o gnd vcc i/o pd2/i/o i/o i/o i/o i/o i/o i/o vcc i/oe2/gck2 gclr/i i/oe1 gck1/i gnd gck3 i/o atf1502se(l) atf1504se(l) 25 atf1502se 2401d?pld?09/02 oe (1, 2) global oe pins gclr global clear pin gclk (1, 2, 3) global clock pins pd (1, 2) power-down pins tdi, tms, tck, tdo jtag pins used for boundary-scan testing or in-system programming gndint ground pins for the internal device logic gndio ground pins for the i/o drivers vccint vcc pins for the internal device logic (+3.3v) vccio vcc for the i/o drivers atf1502se(l) dedicated pinouts dedicated pin 44-plcc j-lead 44-lead tqfp input/gclk1 43 37 input/gclr 139 input/oe1 44 38 input/oe2/gclk2 2 40 i/o/gclk3 41 35 i/o/pd (1,2) 11,25 5,19 i/o/tdi (jtag) 7 1 i/o/tms (jtag) 13 7 i/o/tck (jtag) 32 26 i/o/tdo (jtag) 38 32 gndint 22, 42 16, 36 gndio 10,30 4,24 vccint 3, 23 17, 41 vccio 15,35 9,29 # of signal pins 36 36 # user i/o pins 32 32 26 atf1502se 2401d?pld?09/02 atf1502se(l) i/o pinouts mc plc 44-lead plcc 44-lead tqfp 1a442 2a543 3a644 4/ tdi a71 5a82 6a93 7/ pd1 a115 8a126 9/ tms a137 10 a 14 8 11 a 16 10 12 a 17 11 13 a 18 12 14 a 19 13 15 a 20 14 16 a 21 15 17 b 41 35 18 b 40 34 19 b 39 33 20/ tdo b3832 21 b 37 31 22 b 36 30 23 b 34 28 24 b 33 27 25/ tck b3226 26 b 31 25 27 b 29 23 28 b 28 22 29 b 27 21 30 b 26 20 31/ pd2 b2519 32 b 24 18 27 atf1502se 2401d?pld?09/02 using ?c? product for industrial to use commercial product for industrial temperature ranges, downgrade one speed grade from the ?i? to the ?c? device, and de-rate power by 30%. atf1502se(l) ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 5.0 3.2 250 atf1502se-5 ac44 atf1502se-5 jc44 44a 44j commercial (0 cto70 c) 6.0 3.5 200 atf1502se-6 ac44 atf1502se-6 jc44 44a 44j commercial (0 cto70 c) 7.5 4.3 167 atf1502se-7 ac44 atf1502se-7 jc44 44a 44j commercial (0 cto70 c) atf1502se-7 ai44 atf1502se-7 ji44 44a 44j industrial (-40 cto+85 c) 10 5.0 125 atf1502se-10 ac44 atf1502se-10 jc44 44a 44j commercial (0 cto70 c) atf1502se-10 ai44 atf1502se-10 ji44 44a 44j industrial (-40 cto+85 c) 15 8.0 77 atf1502sel-15 ac44 atf1502sel-15 jc44 44a 44j commercial (0 cto70 c) package type 44a 44-lead, thin plastic gull wing quad flatpack (tqfp) 44j 44-lead, plastic j-leaded chip carrier (plcc) 28 atf1504se(l) 2401d?pld?09/02 ac characteristics (1) atf1504se(l) symbol parameter se -5 se -6 se -7 se -10 sel -15 (6) unit min max min max min max min max min max t pd1 input or feedback to non- registered output 5.0 6.0 7.5 10 15 ns t pd2 i/o input or feedback to non- registered feedback 5.0 6.0 7.5 10 12 ns t su global clock setup time 2.9 3.6 6.0 7.0 11 ns t h global clock hold time 0.0 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 2.5 3.0 3.0 3.0 ns t fh global clock hold of fast input 0.0 0.0 0.5 0.5 1.0 ns t co1 global clock to output delay 3.2 4.0 4.5 5.0 9.0 ns t ch global clock high time 2.0 2.5 3.0 4.0 5.0 ns t cl global clock low time 2.0 2.5 3.0 4.0 5.0 ns t asu arrayclocksetuptime0.70.92.02.05.0 ns t ah array clock hold time 1.8 2.9 2.0 3.0 4.0 ns t aco1 array clock output delay 5.4 6.7 7.5 10.0 15 ns t ach array clock high time 2.5 2.5 3.0 4.0 6.0 ns t acl array clock low time 2.5 2.5 3.0 4.0 6.0 ns t cnt minimum clock global period 5.7 7.1 8.0 10 13 ns f cnt (3) maximum internal global clock frequency 176 141 125 100 77 mhz t acnt minimum array clock period 5.7 7.1 8.0 10 13 ns f acnt (4) maximum internal array clock frequency 176 141 125 100 77 mhz f max (5) maximum clock frequency 250 200 167 125 77 mhz t in input pad and buffer delay 0.2 0.2 0.5 0.5 1.0 ns t io i/o input pad and buffer delay 0.2 0.2 0.5 0.5 1.0 ns t fin fast input delay 2.2 2.6 1.0 1.0 2.0 ns t sexp foldback term delay 3.1 3.8 4.0 5.0 8.0 ns t pexp cascade logic delay 0.9 1.1 0.8 0.8 1.0 ns t lad logic array delay 2.6 3.2 3.0 5.0 6.0 ns t lac logic control delay 2.5 3.2 3.0 5.0 6.0 ns t ioe internal output enable delay 0.7 0.8 2.0 2.0 3.0 ns t od1 output buffer and pad delay (slow slew rate = off; v ccio = 5v; c l =35pf) 0.2 0.3 2.0 1.5 2.5 ns 29 atf1504se(l) 2401d?pld?09/02 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad ,t lac ,t ic ,t acl and t sexp parameters for macrocells running in the reduced- power mode. 3. f cnt is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a pia fan-out of one logic block (16 macrocells). f cnt is also the export control maximum flip-flop toggle rate, f tog . 4. f acnt is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a pia fan-out of one logic block (16 macrocells). 5. f max is the fastest available frequency for pipelined data. 6. for clocked applications and frequencies above f critical , or, non-clocked applications with dormant times less than 1/f crit- ical , the device will achieve the speeds of the ?10 column. see ?input transition detection/ automatic power down? on page 8. t od2 output buffer and pad delay (slow slew rate = off; v ccio = 3.3v; c l =35pf) 0.7 0.8 2.5 2.0 3.0 ns t od3 output buffer and pad delay (slowslewrate=on;v ccio =5v or 3.3v; c l =35pf) 5.2 5.3 7.0 5.5 6.0 ns t zx1 output buffer enable delay (slow slew rate = off; v ccio = 5v; c l =35pf) 4.0 4.0 4.0 5.0 7.0 ns t zx2 output buffer enable delay (slow slew rate = off; v ccio = 3.3v; c l =35pf) 4.5 4.5 4.5 5.5 7.0 ns t zx3 output buffer enable delay (slowslewrate=on;v ccio =5v or 3.3v; c l =35pf) 9.0 9.0 9.0 9.0 10 ns t xz output buffer disable delay (c l =5pf) 4.0 4.0 4.0 5.0 6.0 ns t su register setup time 0.8 1.0 3.0 2.0 5.0 ns t h register hold time 1.7 2.0 2.0 3.0 4.0 ns t fsu register setup time of fast input 1.9 1.8 3.0 3.0 5.0 ns t fh register hold time of fast input 0.6 0.7 0.5 0.5 2.0 ns t rd register delay 1.2 1.6 1.0 2.0 2.0 ns t comb combinatorial delay 0.9 1.0 1.0 2.0 2.0 ns t ic array clock delay 2.7 3.3 3.0 5.0 6.0 ns t en register enable time 2.6 3.2 3.0 5.0 6.0 ns t glob global control delay 1.6 1.9 1.0 1.0 2.0 ns t pre register preset time 2.0 2.4 2.0 3.0 4.0 ns t clr register clear time 2.0 2.4 2.0 3.0 4.0 ns t uim switch matrix delay 1.1 1.3 1.0 1.0 2.0 ns t rpa (2) reduced power adder 8.0 9.0 1.0 11 13 ns ac characteristics (1) atf1504se(l) (continued) symbol parameter se -5 se -6 se -7 se -10 sel -15 (6) unit min max min max min max min max min max 30 atf1504se(l) 2401d?pld?09/02 stand-by i cc vs. supply voltage (t a =25c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.54.85.05.35.5 supply voltage (v) i cc (a) tbd supply current vs. input frequency (v cc =5.0v,t a = 25c) 0.000 20.000 40.000 60.000 80.000 100.000 120.000 140.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz ) i cc (ma) tbd output source current vs. supply voltage (v oh =2.4v) -50 -40 -30 -20 -10 0 4.04.55.05.56.0 supply voltage (v) i oh (ma) tbd output sink current vs. supply voltage (v ol =0.5v) 36 38 40 42 44 46 48 4.0 4.5 5.0 5.5 6.0 supply voltage (v) iol (ma) tbd normalized i cc vs. temp 0.4 0.6 0.8 1.0 1.2 1.4 -40.0 0.0 25.0 75.0 temperature (c) normalized icc tbd supply current vs. input frequency (v cc =5.0v,t a = 25c) 0.000 0.200 0.400 0.600 0.800 1.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. output voltage (v cc =5.0v,t a = 25c) -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 v oh (v) i oh (ma) tbd output sink current vs. output voltage (v cc =5.0v,t a = 25c) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) i ol (ma) tbd 31 atf1504se(l) 2401d?pld?09/02 input clamp current vs. input voltage (v cc =5.0v,t a =35c) -120 -100 -80 -60 -40 -20 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 input voltage (v) input current (ma) tbd normalized t pd vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t pd tbd normalized t co vs. vcc 0.8 0.9 1.0 1.1 1.2 1.3 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t co tbd normalized t su vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t su tbd input current vs. input voltage (v cc =5.0v,t a = 25c) -30 -20 -10 0 10 20 30 40 0.0 1.0 2.0 3.0 4.0 5.0 6.0 input voltage (v) input current (ua) tbd normalized t pd vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (c) normalized t pd tbd normalized t co vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (v) normalized t co tbd normalized t su vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized t co tbd 32 atf1504se(l) 2401d?pld?09/02 delta t pd vs. output loading -2 0 2 4 6 8 0 50 100 150 200 250 300 output loading (pf) delta t pd (ns) tbd delta t pd vs. # of output switching -0.5 -0.4 -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t pd (ns) tbd delta t co vs. output loading 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 50 100 150 200 250 300 number of outputs loading delta t co (ns) tbd delta t co vs. # of output switching -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t co (ns) tbd 33 atf1504se(l) 2401d?pld?09/02 atf1504se(l) pinouts 44-lead tqfp ? top view 44-lead plcc ? top view 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 i/o/tdi i/o i/o gnd pd1/i/o i/o tms/i/o i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 i/o i/o i/o i/o gnd vcc i/o pd2/i/o i/o i/o i/o i/o i/o i/o vcc i/oe2/gck2 gclr/i i/oe1 gck1/i gnd gck3 i/o atf1502se(l) atf1504se(l) 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 tdi/i/o i/o i/o gnd pd1/i/o i/o i/o/tms i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 i/o i/o i/o i/o gnd vcc i/o pd2/i/o i/o i/o i/o i/o i/o i/o vcc gck2/oe2/i gclr/i oe1/i gck1/i gnd i/o/gclk3 i/o atf1502se(l) atf1504se(l) 34 atf1504se(l) 2401d?pld?09/02 84-lead plcc ? top view 100-lead tqfp ? top view 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 i/o/pd1 vccio i/o/tdi i/o i/o i/o i/o gnd i/o i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o i/o i/o gnd i/o i/o gnd i/o/tdo i/o i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o i/o i/o 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o/pd2 i/o gnd i/o i/o i/o i/o i/o vccio i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o atf1504se(l) atf1508se(l) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o/pd1 i/o vccio i/o/tdi i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o/tdo i/o i/o i/o i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o vccio 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 33 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 gnd i/o i/o i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o/pd2 i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o i/o i/o i/o atf1508se(l) 35 atf1504se(l) 2401d?pld?09/02 oe (1, 2) global oe pins gclr global clear pin gclk (1, 2, 3) global clock pins pd (1, 2) power-down pins tdi, tms, tck, tdo jtag pins used for boundary-scan testing or in-system programming gndint ground pins for the internal device logic gndio ground pins for the i/o pins vccint vcc pins for the internal device logic vccio vcc for the i/o drivers atf1504se(l) dedicated pinouts dedicated pin 44-lead tqfp 44-lead plcc 84-lead plcc 100-lead tqfp input/gclk137438387 input/gclr 39 1 1 89 input/oe1 38448488 input/oe2/gclk2 40 2 2 90 i/o/gclk3 35418185 i/o/pd (1,2) 5, 19 11, 25 20, 46 12, 42 i/o/tdi(jtag)1 7144 i/o/tms (jtag) 7 13 23 15 i/o/tck(jtag)26326262 i/o/tdo(jtag)32387173 gndint 16, 36 22, 44 42, 82 38, 86 gndio 4, 24 10, 30 7, 18, 32,47, 69, 72 11, 26, 43, 59, 74, 95 vccint 17, 41 3, 23 3, 43 39, 91 vccio 9, 29 15, 35 13, 26, 33, 53, 66, 78 3, 18, 34, 51, 66, 82 n/c - - - 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 #ofsignalpins36366868 # user i/o pins 32 32 64 64 36 atf1504se(l) 2401d?pld?09/02 atf1504se(l) i/o pinouts mc plc 44-lead plcc 44-lead tqfp 84-lead plcc 100-lead tqfp mc plc 44-lead plcc 44-lead tqfp 84-lead plcc 100-lead tqfp 1 a 12 6 22 14 33 c 24 18 44 40 2 a - - 21 13 34 c - - 45 41 3 a/ pd1 11 5 201235 c/ pd2 25 19 46 42 4 a 9 3 18 10 36 c 26 20 48 44 5 a 8 2 17 9 37 c 27 21 49 45 6a--16838c--5046 7a--15639c--5147 8/ tdi a 7 1 14 4 40 c 28 22 52 48 9 a - - 1210041 c 29235452 10 a - - 119942 c - - 5554 11 a 6 44 10 98 43 c - - 56 56 12 a - - 9 97 44 c - - 57 57 13 a - - 8 96 45 c - - 58 58 14 a 5 43 6 94 46 c 31 25 60 60 15 a - - 5 93 47 c - - 61 61 16 a 4 42 4 92 48/ tck c 32266262 17 b 21 15 41 37 49 d 33 27 63 63 18 b - - 403650 d - - 6464 19 b 20 14 39 35 51 d 34 28 65 65 20 b 19 13 37 33 52 d 36 30 67 67 21 b 18 12 36 32 53 d 37 31 68 68 22 b - - 353154 d - - 6969 23 b - - 343055 d - - 7071 24 b 17113329 56/ tdo d 38327173 25 b 16 10 31 25 57 d 39 33 73 75 26 b - - 302358 d - - 7476 27 b - - 292159 d - - 7579 28 b - - 282060 d - - 7680 29 b - - 271961 d - - 7781 30 b 14 8 25 17 62 d 40 34 79 83 31 b - - 241663 d - - 8084 32/ tms b 13 7 23 15 64 d/ gclk3 41 35 81 85 37 atf1504se(l) 2401d?pld?09/02 using ?c? product for industrial to use commercial product for industrial temperature ranges, down grade one speed grade from the ?i? to the ?c? device, and de-rate power by 30%. atf1504se(l) ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 5.0 3.2 250 atf1504se-5 ac44 atf1504se-5 jc44 atf1504se-5 jc84 atf1504se-5 ac100 44a 44j 84j 100a commercial (0 cto70 c) 6.0 4.0 200 atf1504se-6 ac44 atf1504se-6 jc44 atf1504se-6 jc84 atf1504se-6 ac100 44a 44j 84j 100a commercial (0 cto70 c) 7.5 4.5 167 atf1504se-7 ac44 atf1504se-7 jc44 atf1504se-7 jc84 atf1504se-7 ac100 44a 44j 84j 100a commercial (0 cto70 c) atf1504se-7 ai44 atf1504se-7 ji44 atf1504se-7 j84 atf1504se-7 ai100 44a 44j 84j 100a industrial (-40 cto+85 c) 10 5.0 125 atf1504se-10 ac44 atf1504se-10 jc44 atf1504se-10 jc84 atf1504se-10 ac100 44a 44j 84j 100a commercial (0 cto70 c) atf1504se-10 ai44 atf1504se-10 ji44 atf1504se-10 ji84 atf1504se-10 ai100 44a 44j 84j 100a industrial (-40 cto+85 c) 15 9.0 77 ATF1504SEL-15 ac44 ATF1504SEL-15 jc44 ATF1504SEL-15 jc84 ATF1504SEL-15 ac100 44a 44j 84j 100a commercial (0 cto70 c) package type 44a 44-lead, thin plastic gull wing quad flatpack (tqfp) 44j 44-lead, plastic j-leaded chip carrier (plcc) 84j 84-lead, plastic j-leaded chip carrier (plcc) 100a 100-lead, very thin plastic gull wing quad flatpack (tqfp) 38 atf1508se(l) 2401d?pld?09/02 ac characteristics (1) atf1508se(l) symbol parameter se -6 se -7 se -10 sel -15 (6) unit min max min max min max min max t pd1 input or feedback to non-registered output 6 7.5 10 15 ns t pd2 i/o input or feedback to non-registered feedback 6 7.5 10 15 ns t su global clock setup time 3.4 6.0 7.0 11 ns t h global clock hold time 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 3.0 ns t fh global clock hold of fast input 0 0.5 0.5 1 ns t co1 global clock to output delay 4.0 4.5 5.0 8.0 ns t ch global clock high time 3 3.0 4.0 5.0 ns t cl global clock low time 3 3.0 4.0 5.0 ns t asu array clock setup time 0.9 3.0 2.0 4.0 ns t ah array clock hold time 1.8 2.0 5.0 4.0 ns t aco1 array clock output delay 6.5 7.5 10 15 ns t ach array clock high time 3.0 3 4.0 6.0 ns t acl array clock low time 3.0 3 4.0 6.0 ns t cnt minimum clock global period 6.8 8.0 10 13 ns f cnt (3) maximum internal global clock frequency 150 125 100 77 mhz t acnt minimum array clock period 6.8 8.0 10 13 ns f acnt (4) maximum internal array clock frequency 150 125 100 77 mhz f max (5) maximum clock frequency 167 167 125 100 mhz t in input pad and buffer delay 0.2 0.5 0.5 2.0 ns t io i/o input pad and buffer delay 0.2 0.5 0.5 2.0 ns t fin fast input delay 2.6 1.0 1.0 2.0 ns t sexp foldback term delay 3.7 4.0 5.0 8.0 ns t pexp cascade logic delay 1.1 0.8 0.0 1.0 ns t lad logic array delay 3.0 3.0 5.0 6.0 ns t lac logic control delay 3.0 3.0 5.0 6.0 ns t ioe internal output enable delay 0.7 2.0 2.0 3.0 ns t od1 output buffer and pad delay (slow slew rate = off; v ccio =5v;c l =35pf) 0.4 2.0 1.5 4.0 ns t od2 output buffer and pad delay (slow slew rate = off; v ccio =3.3v;c l =35pf) 0.9 2.5 2.0 5.0 ns t od3 output buffer and pad delay (slow slew rate = on; v ccio =5vor3.3v; c l =35pf) 5.4 7.0 5.5 8.0 ns t zx1 output buffer enable delay (slow slew rate = off; v ccio =5v;c l =35pf) 4.0 4.0 5 6.0 ns 39 atf1508se(l) 2401d?pld?09/02 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad ,t lac ,t ic ,t acl and t sexp parameters for macrocells running in the reduced- power mode. 3. f cnt is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a pia fan-out of one logic block (16 macrocells). f cnt is also the export control maximum flip-flop toggle rate, f tog . 4. f acnt is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a pia fan-out of one logic block (16 macrocells). 5. f max is the fastest available frequency for pipelined data. 6. for clocked applications and frequencies above f critical , or, non-clocked applications with dormant times less than 1/f crit- ical , the device will achieve the speeds of the ?10 column. see ?input transition detection/ automatic power down? on page 8. t zx2 output buffer enable delay (slow slew rate = off; v ccio =3.3v;c l =35pf) 4.5 4.5 5.5 7.0 ns t zx3 output buffer enable delay (slow slew rate = on; v ccio =5vor3.3v; c l =35pf) 99910.0ns t xz output buffer disable delay (c l = 5 pf) 4 4 5 6.0 ns t su register setup time 1.0 3.0 2.0 4.0 ns t h register hold time 1.7 2.0 5.0 4.0 ns t fsu register setup time of fast input 1.9 3.0 3.0 2.0 ns t fh register hold time of fast input 0.6 0.5 0.5 1.0 ns t rd register delay 1.4 1.0 2.0 1.0 ns t comb combinatorial delay 1.0 1.0 2.0 1.0 ns t ic array clock delay 3.1 3.0 5.0 6.0 ns t en register enable time 3.0 3.0 5.0 6.0 ns t glob global control delay 2.0 1.0 1.0 1.0 ns t pre register preset time 2.4 2.0 3.0 4.0 ns t clr register clear time 2.4 2.0 3.0 4.0 ns t uim switch matrix delay 1.4 1.0 1.0 2.0 ns t rpa (2) reduced power adder 10 10 11 13 ns ac characteristics (1) atf1508se(l) (continued) symbol parameter se -6 se -7 se -10 sel -15 (6) unit min max min max min max min max 40 atf1508se(l) 2401d?pld?09/02 stand-by i cc vs. supply voltage (t a =25c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 4.8 5.0 5.3 5.5 supply voltage (v) i cc (a) tbd supply current vs. input frequency (v cc =5.0v,t a = 25c) 0.000 20.000 40.000 60.000 80.000 100.000 120.000 140.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. supply voltage (v oh =2.4v) -50 -40 -30 -20 -10 0 4.0 4.5 5.0 5.5 6.0 supply voltage (v) i oh (ma) tbd output sink current vs. supply voltage (v ol =0.5v) 36 38 40 42 44 46 48 4.0 4.5 5.0 5.5 6.0 supply voltage (v) iol (ma) tbd normalized i cc vs. temp 0.4 0.6 0.8 1.0 1.2 1.4 -40.0 0.0 25.0 75.0 temperature (c) normalized icc tbd supply current vs. input frequency (v cc =5.0v,t a = 25c) 0.000 0.200 0.400 0.600 0.800 1.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. output voltage (v cc =5.0v,t a = 25c) -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 v oh (v) i oh (ma) tbd output sink current vs. output voltage (v cc =5.0v,t a = 25c) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) i ol (ma) tbd 41 atf1508se(l) 2401d?pld?09/02 input clamp current vs. input voltage (v cc =5.0v,t a =35c) -120 -100 -80 -60 -40 -20 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 input voltage (v) input current (ma) tbd normalized t pd vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t pd tbd normalized t co vs. vcc 0.8 0.9 1.0 1.1 1.2 1.3 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t co tbd normalized t su vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t su tbd input current vs. input voltage (v cc =5.0v,t a = 25c) -30 -20 -10 0 10 20 30 40 0.0 1.0 2.0 3.0 4.0 5.0 6.0 input voltage (v) input current (ua) tbd normalized t pd vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (c) normalized t pd tbd normalized t co vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (v) normalized t co tbd normalized t su vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized t co tbd 42 atf1508se(l) 2401d?pld?09/02 delta t pd vs. output loading -2 0 2 4 6 8 0 50 100 150 200 250 300 output loading (pf) delta t pd (ns) tbd delta t pd vs. # of output switching -0.5 -0.4 -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t pd (ns) tbd delta t co vs. output loading 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 50 100 150 200 250 300 number of outputs loading delta t co (ns) tbd delta t co vs. # of output switching -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t co (ns) tbd 43 atf1508se(l) 2401d?pld?09/02 atf1508se(l) pinouts 84-lead plcc ? top view 100-lead tqfp ? top view 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 i/o/pd1 vccio i/o/tdi i/o i/o i/o i/o gnd i/o i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o i/o i/o gnd i/o i/o gnd i/o/tdo i/o i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o i/o i/o 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o/pd2 i/o gnd i/o i/o i/o i/o i/o vccio i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o atf1504se(l) atf1508se(l) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o/pd1 i/o vccio i/o/tdi i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o/tdo i/o i/o i/o i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o vccio 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 33 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 gnd i/o i/o i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o/pd2 i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o i/o i/o i/o atf1508se(l) 44 atf1508se(l) 2401d?pld?09/02 100-lead pqfp ? top view 160-lead tqfp ? top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc nc i/o i/o vccio i/o/tdi nc i/o nc i/o i/o i/o gnd i/o/pd1 i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o nc i/o nc i/o gnd nc nc nc nc i/o i/o gnd i/o/tdo nc i/o nc i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o nc i/o nc i/o vccio nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o i/o/pd2 gnd i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o 1 20 120 101 160 141 41 60 80 atf1508se(l) 45 atf1508se(l) 2401d?pld?09/02 oe (1,2) global oe pins. gclr global clear pin. gclk (1,2,3) global clock pins. tdi, tms, tck, tdo jtag pins used for in system programming or boundary-scan testing. gndint ground pins for the internal device logic. gndio ground pins for the i/o drivers. vccint vcc pins for the internal device logic. vccio vcc pins for the i/o drivers. atf1508se(l) dedicated pinouts dedicated pin 84-plcc j- lead 100-pin tqfp 100-pin pqfp 160-lead pqfp input/gclk1 83 87 89 139 input/gclr 1 89 91 141 input/oe1 84 88 90 140 input/oe2/gck2 2 90 92 142 i/o/gclk3 81 85 87 137 i/o pd (1,2) 12, 45 1,41 3, 43 63,159 tdi (jtag) 14 4 6 9 tms (jtag) 23 15 17 22 tck (jtag) 62 62 64 99 tdo (jtag) 71 73 75 112 gndint 42, 82 38,86 40,88 60,138 gndio 7, 19, 32, 47, 59, 72 11, 26, 43, 59, 74, 95 13, 28, 61, 76, 45, 97 17, 42,113, 66, 95,148 vccint 3, 43 39, 91 41,93 61,143 vccio 13, 26, 38, 53, 66, 78 3, 18, 34, 51, 66, 82 5,20,36,53,68,84 8,26,55,79,104,133 no connect - - ? 1,2,3,4,5,6,7,34,35,36, 37,38,39,40,44,45,46, 47,74,75,76,77,81,82, 83,84,85,86,87,114, 115,116,117,118,119, 120,124,125,126,127, 154,155,156,157 # of signal pins 68 84 84 100 # of user i/o pins 64 80 80 96 46 atf1508se(l) 2401d?pld?09/02 atf1508se(l) i/o pinouts mc plb 84-plcc j-lead 100-lead pqfp 100-lead tqfp 160-lead pqfp mc plb 84-plcc j-lead 100-lead pqfp 100-lead tqfp 160-lead pqfp 1a?4216033c?272541 2a????34c???? 3/ pd1 a 12 3 115935 c 31262433 4a???15836c???32 5 a 11 2 100 153 37 c 30 25 23 31 6 a 10 1 9915238 c 29242230 7a????39c???? 8 a 9 100 98 151 40 c 28 23 21 29 9 a ? 99 97 150 41 c ? 22 20 28 10a????42c???? 11 a 8 98 96 149 43 c 27 21 19 27 12 a ? ? ? 147 44 c ? ? ? 25 13 a 6 96 94 146 45 c 25 19 17 24 14 a 5 95 93 145 46 c 24 18 16 23 15a????47c???? 16 a 4 94 92 144 48/ tms c 23171522 17 b 22 16 14 21 49 d 41 39 37 59 18b????50d???? 19 b 21 15 13 20 51 d 40 38 36 58 20 b ? ? ? 19 52 d ? ? ? 57 21 b 20 14 12 18 53 d 39 37 35 56 22 b ? 12 10 16 54 d ? 35 33 54 23b????55d???? 24 b 1811 9 15 56 d 37343253 25 b 1710 8 14 57 d 36333152 26b????58d???? 27 b 16 9 7 13 59 d 35 32 30 51 28 b ? ? ? 12 60 d ? ? ? 50 29 b 15 8 6 11 61 d 34 31 29 49 30 b ? 7 5 10 62 d ? 30 28 48 31b????63d???? 32/ tdi b/ 14 6 4 9 64 d 33 29 27 43 47 atf1508se(l) 2401d?pld?09/02 65 e 44 42 40 62 97 g 63 65 63 100 66e????98g???? 67/ pd2 e 45 43 41 63 99 g 64 66 64 101 68 e ? ? ? 64 100 g ? ? ? 102 69 e 46 44 42 65 101 g 65 67 65 103 70 e ? 46 44 67 102 g ? 69 67 105 71e????103g???? 72 e 48 47 45 68 104 g 67 70 68 106 73 e 49 48 46 69 105 g 68 71 69 107 74e????106g???? 75 e 50 49 47 70 107 g 69 72 70 108 76 e ? ? ? 71 108 g ? ? ? 109 77 e 51 50 48 72 109 g 70 73 71 110 78 e ? 51 49 73 110 g ? 74 72 111 79e????111g???? 80 e 52 52 50 78 112/ tdo g 71 75 73 112 81 f ? 54 52 80 113 h ? 77 75 121 82f????114h???? 83 f 54 55 53 88 115 h 73 78 76 122 84 f ? ? ? 89 116 h ? ? ? 123 85 f 55 56 54 90 117 h 74 79 77 128 86 f 56 57 55 91 118 h 75 80 78 129 87f????119h???? 88 f 57 58 56 92 120 h 76 81 79 130 89 f ? 59 57 93 121 h ? 82 80 131 90f????122h???? 91 f 58 60 58 94 123 h 77 83 81 132 92 f ? ? ? 96 124 h ? ? ? 134 93 f 60 62 60 97 125 h 79 85 83 135 94 f 61 63 61 98 126 h 80 86 84 136 95f????127h???? 96 f/ tck 62 64 62 99 128/ gclk3 h 81 87 85 137 atf1508se(l) i/o pinouts (continued) mc plb 84-plcc j-lead 100-lead pqfp 100-lead tqfp 160-lead pqfp mc plb 84-plcc j-lead 100-lead pqfp 100-lead tqfp 160-lead pqfp 48 atf1508se(l) 2401d?pld?09/02 using ?c? product for industrial to use commercial product for industrial temperature ranges, down-grade one speed grade from the ?i? to the ?c? device and de-rate power by 30%. atf1508se(l) ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 6.0 4.0 167 atf1508se-5 jc84 atf1508se-5 ac100 atf1508se-5 qc100 atf1508se-5 qc160 84j 100a 100q4 160q1 commercial (0 cto70 c) 7.5 4.5 167 atf1508se-7 jc84 atf1508se-7 ac100 atf1508se-7 qc100 atf1508se-7 qc160 84j 100a 100q4 160q1 commercial (0 cto70 c) atf1508se-7 ji84 atf1508se-7 ai100 atf1508se-7 qi100 atf1508se-7 qi160 84j 100a 100q4 160q1 industrial (-40 cto+85 c) 10 5.0 125 atf1508se-10 jc84 atf1508se-10 ac100 atf1508se-10 qc100 atf1508se-10 qc160 84j 100a 100q4 160q1 commercial (0 cto70 c) atf1508se-10 ji84 atf1508se-10 ai100 atf1508se-10 qi100 atf1508se-10 qi160 84j 100a 100q4 160q1 industrial (-40 cto+85 c) 15 8.0 100 atf1508sel-15 jc84 atf1508sel-15 ac100 atf1508sel-15 qc100 atf1508sel-15 qc160 84j 100a 100q4 160q1 commercial (0 cto70 c) package type 84j 84-lead, plastic j-leaded chip carrier (plcc) 100a 100-lead, very thin plastic gull wing quad flatpack (tqfp) 100q4 100-lead, plastic quad pin flat package (pqfp) 160q1 160-lead, plastic quad pin flat package (pqfp) 49 atf1516se(l) 2401d?pld?09/02 ac characteristics (1) atf1516se(l) symbol parameter se -7 se -10 sel -15 (6) unit min max min max min max t pd1 input or feedback to non-registered output 7.5 10 15 ns t pd2 i/o input or feedback to non-registered feedback 7.5 10 12 ns t su global clock setup time 3.9 7.0 11 ns t h global clock hold time 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 3.9 3.0 3.0 ns t fh global clock hold of fast input 0.0 0.5 1 ns t co1 global clock to output delay 4.7 5.0 8.0 ns t ch global clock high time 3.0 4.0 5.0 ns t cl global clock low time 3.0 4.0 5 ns t asu array clock setup time 0.8 2.0 4.0 ns t ah array clock hold time 1.9 3.0 4.0 ns t aco1 array clock output delay 7.3 1 10 15 ns t ach array clock high time 3.0 4 6 ns t acl array clock low time 3.0 4 6 ns t cnt minimum clock global period 7.8 10 13 ns f cnt (3) maximum internal global clock frequency 130 100 77 mhz t acnt minimum array clock period 7.8 10 13 ns f acnt (4) maximum internal array clock frequency 130 100 77 mhz f max (5) maximum clock frequency 167 125 100 mhz t in input pad and buffer delay 0.3 0.5 2.0 ns t io i/o input pad and buffer delay 0.3 0.5 2.0 ns t fin fast input delay 3.4 1.0 2.0 ns t sexp foldback term delay 3.9 5.0 8.0 ns t pexp cascade logic delay 1.1 0.8 1.0 ns t lad logic array delay 2.6 5.0 6.0 ns t lac logic control delay 2.6 5.0 6.0 ns t ioe internal output enable delay 0.8 2.0 3.0 ns t od1 output buffer and pad delay (slow slew rate = off; v ccio =5v;c l =35pf) 0.5 1.5 4.0 ns t od2 output buffer and pad delay (slow slew rate = off; v ccio =3.3v;c l =35pf) 1.0 2.0 5.0 ns t od3 output buffer and pad delay (slow slew rate = on; v ccio =5vor3.3v; c l =35pf) 5.5 5.5 8.0 ns t zx1 output buffer enable delay (slow slew rate = off; v ccio =5v;c l =35pf) 4.0 5.0 6.0 ns 50 atf1516se(l) 2401d?pld?09/02 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad ,t lac ,t ic ,t acl and t sexp parameters for macrocells running in the reduced- power mode. 3. f cnt is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a pia fan-out of one logic block (16 macrocells). f cnt is also the export control maximum flip-flop toggle rate, f tog . 4. f acnt is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a pia fan-out of one logic block (16 macrocells). 5. f max is the fastest available frequency for pipelined data. 6. for clocked applications and frequencies above f critical , or, non-clocked applications with dormant times less than 1/f crit- ical , the device will achieve the speeds of the ?10 column. see ?input transition detection/ automatic power down? on page 8. t zx2 output buffer enable delay (slow slew rate = off; v ccio =3.3v;c l =35pf) 4.5 5.5 7.0 ns t zx3 output buffer enable delay (slow slew rate = on; v ccio =5vor3.3v;c l =35 pf) 9.0 9.0 10.0 ns t xz output buffer disable delay (c l = 5 pf) 4.0 5.0 6.0 ns t su register setup time 1.1 2.0 4.0 ns t h register hold time 1.6 3.0 4.0 ns t fsu register setup time of fast input 2.4 3.0 2.0 ns t fh register hold time of fast input 0.6 0.5 1.0 ns t rd register delay 1.1 2.0 1.0 ns t comb combinatorial delay 1.1 2.0 1.0 ns t ic array clock delay 2.9 5.0 6.0 ns t en register enable time 2.6 5.0 6.0 ns t glob global control delay 2.8 1.0 1.0 ns t pre register preset time 2.7 3.0 4.0 ns t clr register clear time 2.7 3.0 4.0 ns t uim switch matrix delay 3.0 1.0 2.0 ns t rpa reduced power adder (2) 10 11 13 ns ac characteristics (1) atf1516se(l) (continued) symbol parameter se -7 se -10 sel -15 (6) unit min max min max min max 51 atf1516se(l) 2401d?pld?09/02 stand-by i cc vs. supply voltage (t a =25c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 4.8 5.0 5.3 5.5 supply voltage (v) i cc (a) tbd supply current vs. input frequency (v cc =5.0v,t a = 25c) 0.000 20.000 40.000 60.000 80.000 100.000 120.000 140.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. supply voltage (v oh =2.4v) -50 -40 -30 -20 -10 0 4.0 4.5 5.0 5.5 6.0 supply voltage (v) i oh (ma) tbd output sink current vs. supply voltage (v ol =0.5v) 36 38 40 42 44 46 48 4.0 4.5 5.0 5.5 6.0 supply voltage (v) iol (ma) tbd normalized i cc vs. temp 0.4 0.6 0.8 1.0 1.2 1.4 -40.0 0.0 25.0 75.0 temperature (c) normalized icc tbd supply current vs. input frequency (v cc =5.0v,t a = 25c) 0.000 0.200 0.400 0.600 0.800 1.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. output voltage (v cc =5.0v,t a = 25c) -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 v oh (v) i oh (ma) tbd output sink current vs. output voltage (v cc =5.0v,t a =25c) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) i ol (ma) tbd 52 atf1516se(l) 2401d?pld?09/02 input clamp current vs. input voltage (v cc =5.0v,t a =35c) -120 -100 -80 -60 -40 -20 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 input voltage (v) input current (ma) tbd normalized t pd vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t pd tbd normalized t co vs. vcc 0.8 0.9 1.0 1.1 1.2 1.3 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t co tbd normalized t su vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t su tbd input current vs. input voltage (v cc =5.0v,t a = 25c) -30 -20 -10 0 10 20 30 40 0.0 1.0 2.0 3.0 4.0 5.0 6.0 input voltage (v) input current (ua) tbd normalized t pd vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (c) normalized t pd tbd normalized t co vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (v) normalized t co tbd normalized t su vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized t co tbd 53 atf1516se(l) 2401d?pld?09/02 delta t pd vs. output loading -2 0 2 4 6 8 0 50 100 150 200 250 300 output loading (pf) delta t pd (ns) tbd delta t pd vs. # of output switching -0.5 -0.4 -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t pd (ns) tbd delta t co vs. output loading 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 50 100 150 200 250 300 number of outputs loading delta t co (ns) tbd delta t co vs. # of output switching -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t co (ns) tbd 54 atf1516se(l) 2401d?pld?09/02 atf1516se(l) dedicated pinouts 208-lead pqfp and rqfp ? top view 1 26 156 131 208 183 53 78 104 atf1516se(l) 55 atf1516se(l) 2401d?pld?09/02 oe (1,2) global oe pins. gclr global clear pin. gclk (1,2,3) global clock pins. tdi, tms, tck, tdo jtag pins used for in system programming or boundary-scan testing. gndint ground pins for the internal device logic. gndio ground pins for the i/o drivers. vccint vcc pins for the internal device logic. vccio vcc pins for the i/o drivers. atf1516se(l) dedicated pinouts dedicated pin 208-pin pqfp 208-pin rqfp input/gclk1 184 184 input/gclr 182 182 input/oe1 183 183 input/oe2/gck2 181 181 i/o/gclk3 tbd tbd i/o pd (1,2) tbd tbd tdi (jtag) 176 176 tms (jtag) 127 127 tck (jtag) 30 30 tdo (jtag) 189 189 gndint 75, 82, 180, 185 75, 82, 180, 185 gndio 14, 32, 50, 72, 94, 116, 134, 152, 174, 200 14, 32, 50, 72, 94, 116, 134, 152, 174, 200 vccint 74, 83, 179, 186 74, 83, 179, 186 vccio 5, 23, 41, 63, 85, 107, 125, 143, 165, 191 5, 23, 41, 63, 85, 107, 125, 143, 165, 191 no connect 1,2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208 1,2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208 # of signal pins 164 164 # of user i/o pins 160 160 56 atf1516se(l) 2401d?pld?09/02 atf1516se(l) i/o pinouts mc plb 208-pin pqfp 208-pin rqrp mc plb 208-pin pqfp 208-pin rqfp 1 a 153 153 33 c 108 108 2a - - 34c - - 3 a 154 154 35 c 109 109 4a - - 36c - - 5 a 159 159 37 c 110 110 6 a 160 160 38 c 111 111 7a - - 39c - - 8 a 161 161 40 c 112 112 9 a 162 162 41 c 113 113 10 a - - 42 c - - 11 a 163 163 43 c 114 114 12 a - - 44 c - - 13 a 164 164 45 c 115 115 14 a 166 166 46 c 117 117 15 a - - 47 c - - 16 a 167 167 48 c 118 118 17 b 141 141 49 d 92 92 18 b - - 50 d - - 19 b 142 142 51 d 93 93 20 b - - 52 d - - 21 b 144 144 53 d 95 95 22 b 145 145 54 d 96 96 23 b - - 55 d - - 24 b 146 146 56 d 97 97 25 b 147 147 57 d 98 98 26 b - - 58 d - - 27 b 148 148 59 d 99 99 28 b - - 60 d - - 29 b 149 149 61 d 100 100 30 b 150 150 62 d 101 101 31 b - - 63 d - - 32 b 151 151 64 d 102 102 57 atf1516se(l) 2401d?pld?09/02 65 e 168 168 97 g 119 119 66 e - - 98 g - - 67 e 169 169 99 g 120 120 68 e - - 100 g - - 69 e 170 170 101 g 121 121 70 e 171 171 102 g 122 122 71 e - - 103 g - - 72 e 172 172 104 g 123 123 73 e 173 173 105 g 124 124 74 e - - 106 g - - 75 e 175 175 107 g 126 126 76 e - - 108 g - - 77 e 176 176 109 g 127 127 78 e 177 177 110 g 128 128 79 e - - 111 g - - 80 e 178 178 112 g 129 129 81 f 130 130 113 h 79 79 82 f - - 114 h - - 83 f 131 131 115 h 80 80 84 f - - 116 h - - 85 f 132 132 117 h 81 81 86 f 133 133 118 h 84 84 87 f - - 119 h - - 88 f 135 135 120 h 86 86 89 f 136 136 121 h 87 87 90 f - - 122 h - - 91 f 137 137 123 h 88 88 92 f - - 124 h - - 93 f 138 138 125 h 89 89 94 f 139 139 126 h 90 90 95 f - - 127 h - - 96 f 140 140 128 h 91 91 atf1516se(l) i/o pinouts (continued) mc plb 208-pin pqfp 208-pin rqrp mc plb 208-pin pqfp 208-pin rqfp 58 atf1516se(l) 2401d?pld?09/02 129 i 197 197 161 k 38 38 130 i - - 162 k - - 131 i 196 196 163 k 37 37 132 i - - 164 k - - 133 i 195 195 165 k 36 36 134 i 194 194 166 k 35 35 135 i - - 167 k - - 136 i 193 193 168 k 34 34 137 i 192 192 169 k 33 33 138 i - - 170 k - - 139 i 190 190 171 k 31 31 140 i - - 172 k - - 141 i 189 189 173 k 30 30 142 i 188 188 174 k 29 29 143 i - - 175 k - - 144 i 187 187 176 k 28 28 145 j 27 27 177 l 78 78 146 j - - 178 l - - 147 j 26 26 179 l 77 77 148 j - - 180 l - - 149 j 25 25 181 l 76 76 150 j 24 24 182 l 73 73 151 j - - 183 l - - 152 j 22 22 184 l 71 71 153 j 21 21 185 l 70 70 154 j - - 186 l - - 155 j 20 20 187 l 69 69 156 j - - 188 l - - 157 j 19 19 189 l 68 68 158 j 18 18 190 l 67 67 159 j - - 191 l - - 160 j 17 17 192 l 66 66 atf1516se(l) i/o pinouts (continued) mc plb 208-pin pqfp 208-pin rqrp mc plb 208-pin pqfp 208-pin rqfp 59 atf1516se(l) 2401d?pld?09/02 193 m 4 4 225 o 49 49 194 m - - 226 o - - 195 m 3 3 227 o 48 48 196 m - - 228 o - - 197 m 206 206 229 o 47 47 198 m 205 205 230 o 46 46 199 m - - 231 o - - 200 m 204 204 232 o 45 45 201 m 203 203 233 o 44 44 202 m - - 234 o - - 203 m 202 202 235 o 43 43 204 m - - 236 o - - 205 m 201 201 237 o 42 42 206 m 199 199 238 o 40 40 207 m - - 239 o - - 208 m 198 198 240 o 39 39 209 n 16 16 241 p 65 65 210 n - - 242 p - - 211 n 15 15 243 p 64 64 212 n - - 244 p - - 213 n 13 13 245 p 62 62 214 n 12 12 246 p 61 61 215 n - - 247 p - - 216 n 11 11 248 p 60 60 217 n 10 10 249 p 59 59 218 n - - 250 p - - 219 n 9 9 251 p 58 58 220 n - - 252 p - - 221 n 8 8 253 p 57 57 222 n 7 7 254 p 56 56 223 n - - 255 p - - 224 n 6 6 256 p 55 55 atf1516se(l) i/o pinouts (continued) mc plb 208-pin pqfp 208-pin rqrp mc plb 208-pin pqfp 208-pin rqfp 60 atf1516se(l) 2401d?pld?09/02 using ?c? product for industrial to use commercial product for industrial temperature ranges, down-grade one speed grade from the ?i? to the ?c? device, and de-rate power by 30%. atf1516se(l) ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 7.5 4.7 167 atf1516se-7 qc208 atf1516se-7 rc208 208q1 208q2 commercial (0 cto70 c) atf1516se-7 qi208 atf1516se-7 ri208 208q1 208q2 industrial (-40 cto+85 c) 10 5.0 125 atf1516se-10 qc208 atf1516se-10 rc208 208q1 208q2 commercial (0 cto70 c) atf1516se-10 qi208 atf1516se-10 ri208 208q1 208q2 industrial (-40 cto+85 c) 15 8.0 100 atf1516sel-15 qc208 atf1516sel-15 rc208 208q1 208q2 commercial (0 cto70 c) package type 208q1 208-lead, 28 x 28 mm body, 2.6 form opt., plastic quad flatpack (pqfp) 208q2 208-lead, 28 x 28 mm body, 2.6 form opt., plastic quad flatpack with heat spreader (pqfp) 61 atf1516se(l) 2401d?pld?09/02 package information 44a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ 62 atf1516se(l) 2401d?pld?09/02 44j?plcc notes: 1. this package conforms to jedec reference ms-018, variation ac. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 4.572 a1 2.286 3.048 a2 0.508 d 17.399 17.653 d1 16.510 16.662 note 2 e 17.399 17.653 e1 16.510 16.662 note 2 d2/e2 14.986 16.002 b 0.660 0.813 b1 0.330 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45 pin no. 1 identifier 1.14(0.045) x 45 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45 max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-lead, plastic j-leaded chip carrier (plcc) b 44j 10/04/01 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 63 atf1516se(l) 2401d?pld?09/02 84j?plcc 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 84j , 84-lead, plastic j-leaded chip carrier (plcc) b 84j 10/04/01 1.14(0.045) x 45 pin no. 1 identifier 1.14(0.045) x 45 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45 max (3x) a a1 b1 d2/e2 b e e1 e d1 d common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-018, variation af. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 4.572 a1 2.286 3.048 a2 0.508 d 30.099 30.353 d1 29.210 29.413 note 2 e 30.099 30.353 e1 29.210 29.413 note 2 d2/e2 27.686 28.702 b 0.660 0.813 b1 0.330 0.533 e 1.270 typ 64 atf1516se(l) 2401d?pld?09/02 100a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100a, 100-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp) c 100a 10/5/2001 pin 1 identifier 0 ? ~7 ? pin 1 l c a1 a2 a d1 d e e1 e b a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.17 0.27 c 0.09 0.20 l 0.45 0.75 e 0.50 typ notes: 1. this package conforms to jedec reference ms-026, variation aed. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.08 mm maximum. common dimensions (unit of measure = mm) symbol min nom max note 65 atf1516se(l) 2401d?pld?09/02 100q4 ? pqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100q4 a 3/29/02 100q4, 100-lead, 14 x 20 mm body, 3.2 form opt., plastic quad flat pack (pqfp) side view top view bottom view e1 d1 d e a2 a1 e b l1 common dimensions (unit of measure = mm) symbol min nom max note a1 0.25 0.50 5 a2 2.50 2.70 2.90 d 23.20 bsc 2 d1 20.00 bsc 3 e 17.20 bsc 2 e1 14.00 bsc 3 e 0.65 bsc b 0.22 0.40 4 l1 1.60 ref notes: 1. this drawing is for general information only. refer to jedec drawing ms-022, variation gc-1, for additional information. 2. to be determined at seating plane. 3. regardless of the relative size of the upper and lower body sections, dimensions d1 and e1 are determined at the largest feature of the body exclusive of mold flash and gate burrs, but including any mismatch between the upper and lower sections of the molded body. 4. dimension b does not include dambar protrusion. the dambar protrusion(s) shall not cause the lead width to exceed b maximum by more than 0.08 mm. dambar cannot be located on the lower radius or the lead foot. 5. a1 is defined as the distance from the seating plane to the lowest point of the package body. 66 atf1516se(l) 2401d?pld?09/02 160q1 ? pqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 160q1 a 3/28/02 160q1, 160-lead, 28 x 28 mm body, 3.2 form opt., plastic quad flat pack (pqfp) e d e1 d1 a2 a1 b l1 e side view top view bottom view common dimensions (unit of measure = mm) symbol min nom max note a1 0.25 0.50 5 a2 3.20 3.40 3.60 d 31.20 bsc 2 d1 28.00 bsc 3 e 31.20 bsc 2 e1 28.00 bsc 3 e 0.65 bsc b 0.22 0.40 4 l1 1.60 ref notes: 1. this drawing is for general information only. refer to jedec drawing ms-022, variation dd-1, for additional information. 2. to be determined at seating plane. 3. regardless of the relative size of the upper and lower body sections, dimensions d1 and e1 are determined at the largest feature of the body exclusive of mold flash and gate burrs, but including any mismatch between the upper and lower sections of the molded body. 4. dimension b does not include dambar protrusion. the dambar protrusion(s) shall not cause the lead width to exceed b maximum by more than 0.08 mm. dambar cannot be located on the lower radius or the lead foot. 5. a1 is defined as the distance from the seating plane to the lowest point of the package body. 67 atf1516se(l) 2401d?pld?09/02 208q1 ? pqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 208q1 b 07/23/02 l1 a2 a1 a1 b d1 d e1 e e side view bottom view top view common dimensions (unit of measure = mm) symbol min nom max note 208q1 , 208-lead (28 x 28 mm body, 2.6 form opt.), plastic quad flat pack (pqfp) a1 0.25 0.50 a2 3.20 3.40 3.60 d 30.60 bsc d1 28.00 bsc 2, 3 e 30.60 bsc e1 28.00 bsc 2, 3 e 0.50 bsc b 0.17 0.27 4 l1 1.30 ref notes: 1. this drawing is for general information only; refer to jedec drawing ms-129, variation fa-1, for proper dimensions, tol erances, datums, etc. 2. the top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. dimensions d1 and e1 do not include mold protrusions. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maxi mum b dimension by more than 0.08 mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07 mm. 68 atf1516se(l) 2401d?pld?09/02 208q2 ? pqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 208q2 a 07/23/02 l1 a2 a1 a1 b d1 d e1 e e side view bottom view top view common dimensions (unit of measure = mm) symbol min nom max note 208q2 , 208-lead (28 x 28 mm body, 2.6 form opt.), plastic quad flat pack (pqfp) a1 0.05 0.25 a2 3.20 3.40 3.60 d 30.60 bsc d1 28.00 bsc 2, 3 e 30.60 bsc e1 28.00 bsc 2, 3 e 0.50 bsc b 0.17 0.27 4 l1 1.30 ref notes: 1. this drawing is for general information only; refer to jedec drawing ms-129, variation fa-2, for proper dimensions, tol erances, datums, etc. 2. the top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. dimensions d1 and e1 do not include mold protrusions. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maxi mum b dimension by more than 0.08 mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07 mm. printed on recycled paper. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 2401d?pld?09/02 xm at m e l is the registered trademark of atmel; logic doubling is the trademark of atmel. other terms and product names may be the trademarks of others. |
Price & Availability of ATF1504SEL
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |